Enabling AI ASICs for Zero Knowledge Proof
A new framework called MORPH runs zero-knowledge proof math on Google's TPUs, hitting up to 10x faster throughput on one key operation than a specialized GPU baseline.

The Thesis
Zero-knowledge proofs (ZKPs) — cryptographic techniques that let one party prove a fact to another without revealing the underlying data — are increasingly used in blockchain scaling and privacy applications, but generating them is expensive. The two most compute-intensive operations inside a ZKP prover are multi-scalar multiplication (MSM) and number-theoretic transforms (NTTs), both of which demand high-precision modular arithmetic that GPUs handle awkwardly. MORPH reformulates these operations so they can run on AI accelerators like Google's TPUs, which are optimized for dense, low-precision matrix math. The core trick is converting modular arithmetic into a form that fits naturally into the matrix multiply units (MXUs) at the heart of a TPU. On one key operation (NTT), TPUv6e8 running MORPH achieves up to 10x higher throughput than GZKP, a dedicated GPU-based ZKP framework, though MSM performance is only comparable rather than superior.
Catalyst
Google's TPUv6e (codenamed Trillium) is the first TPU generation with both the raw matrix throughput and the memory bandwidth profile that makes this reformulation practical. JAX, Google's numerical computing framework, now has mature primitives for the kind of sharding and layout control MORPH relies on. Prior attempts to run ZKP on non-GPU hardware stalled because no clean mapping existed between modular arithmetic and tensor operations — this paper proposes one.
What's New
Prior ZKP acceleration work, including GZKP and various FPGA-based designs, treated GPU or FPGA as the natural target and optimized within those paradigms. Those approaches kept modular arithmetic in its native high-precision, carry-chain form, which is fine for GPUs but does not fit the low-precision matrix units that dominate modern AI chips. MORPH introduces an extended-RNS (Residue Number System) lazy reduction scheme — a way of representing large integers as sets of smaller remainders — that converts the arithmetic into standard low-precision matrix multiplications, plus a layout-stationary dataflow that avoids the expensive memory shuffles that would otherwise negate TPU throughput gains.
The Counter
The 10x NTT speedup is real but narrow. NTT is the smaller of the two main ZKP bottlenecks; MSM typically dominates total proving time, and on MSM MORPH is only 'comparable' to the GPU baseline — which is not a win for a purpose-built framework. The comparison baseline, GZKP, is also not the strongest available: dedicated GPU libraries from teams actively optimizing for ZKP (such as Icicle from Ingonyama) are not benchmarked. TPUs are also not neutral infrastructure — they are Google hardware, not available as spot compute, and their accessibility to the ZKP ecosystem, which runs heavily on permissionless commodity cloud, is genuinely limited. Finally, the ZKP field is moving fast toward proof systems that reduce or eliminate MSM entirely; a framework that optimizes for today's dominant kernels may be targeting a shrinking problem.
Longs
None listed.
Shorts
- GPU-centric ZKP prover services: if TPUs prove cheaper per proof at scale, services built around high-end Nvidia GPU clusters (H100-based prover networks) lose their cost advantage.
- FPGA-based ZKP accelerator startups: bespoke FPGA designs for MSM and NTT become less differentiated if commodity AI ASICs can match their throughput at lower cost.
Enablers (Picks & Shovels)
- JAX (Google's numerical computing framework used for the implementation)
- Google TPUv6e hardware
- XLA compiler (the backend JAX targets for TPU code generation)
- RNS (Residue Number System) arithmetic libraries
Private Watchlist
- Axiom (ZKP infrastructure for Ethereum)
- Succinct Labs (ZKP coprocessor network)
- RiscZero (general-purpose ZKP proving)
- Ingonyama (ZK hardware acceleration)
The Paper
Zero-knowledge proof (ZKP) provers remain costly because multi-scalar multiplication (MSM) and number-theoretic transforms (NTTs) dominate runtime as they need significant computation. AI ASICs such as TPUs provide massive matrix throughput and SotA energy efficiency. We present MORPH, the first framework that reformulates ZKP kernels to match AI-ASIC execution. We introduce Big-T complexity, a hardware-aware complexity model that exposes heterogeneous bottlenecks and layout-transformation costs ignored by Big-O. Guided by this analysis, (1) at arithmetic level, MORPH develops an MXU-centric extended-RNS lazy reduction that converts high-precision modular arithmetic into dense low-precision GEMMs, eliminating all carry chains, and (2) at dataflow level, MORPH constructs a unified-sharding layout-stationary TPU Pippenger MSM and optimized 3/5-step NTT that avoid on-TPU shuffles to minimize costly memory reorganization. Implemented in JAX, MORPH enables TPUv6e8 to achieve up-to 10x higher throughput on NTT and comparable throughput on MSM than GZKP. Our code: https://github.com/EfficientPPML/MORPH.