SCENIC: Stream Computation-Enhanced SmartNIC

The Thesis

SmartNICs — network cards with onboard processors that offload work from the main CPU — sit at the center of modern AI datacenter infrastructure. Today's commercial options (from vendors like Nvidia's BlueField or Marvell's Octeon) offer high bandwidth and software compatibility but are difficult to customize. Research alternatives are usually the opposite: highly programmable but too slow or too incompatible to deploy. SCENIC proposes a third path: treat the NIC's data pipeline as a programmable computing substrate, co-designed with software from the ground up, at full commercial speeds. The catch is that SCENIC is an FPGA-based research prototype, not a shipping product, and the gap between an academic demonstration and a production datacenter deployment is substantial.

Catalyst

AI workloads — particularly distributed training and inference — have made in-network computing a priority, creating demand that neither pure software stacks nor inflexible commercial ASICs fully satisfy. The maturation of high-density FPGAs capable of 200G line-rate processing, combined with standardized RDMA (Remote Direct Memory Access, a method for one machine to read or write another's memory without CPU involvement) interfaces, makes a research prototype at this bandwidth tier feasible today. Open-source hardware toolchains such as Corundum (an open FPGA NIC framework) also lowered the barrier to building a full, OS-integrated network stack.

What's New

Prior research SmartNICs — systems like ClickNP, iPipe, and StRoM — demonstrated programmable in-network processing but typically operated at 10–40G speeds and required custom, non-standard driver interfaces that broke compatibility with ordinary Linux applications. Commercial SmartNICs such as Nvidia's BlueField-3 offer full OS integration and 200G bandwidth but expose only a fixed processing pipeline with limited user customization. SCENIC's claimed advance is delivering both: 200G throughput with offloaded TCP/IP and RDMA, full native Linux and RDMA verb compatibility, and a programmable stream compute layer that sits directly on the data path without requiring application changes.

The Counter

The paper's central claim — that a single open design can match commercial SmartNICs on bandwidth while also being freely customizable — is exactly what every research SmartNIC paper has claimed for a decade. The 200G numbers are real, but they come from an FPGA running at a fraction of the clock speed and a fraction of the density of a production ASIC; the comparison to commercial platforms is therefore somewhat misleading. Nvidia's BlueField and Marvell's Octeon are not just network chips — they are bundled with years of driver hardening, vendor support contracts, and deep integration with hyperscaler software stacks that a fresh open-source project cannot replicate. The use cases demonstrated (collective communication offload, network-to-GPU partitioning) are compelling AI-datacenter scenarios, but they are also exactly the scenarios Nvidia already addresses with its SHARP in-network computing technology on InfiniBand. Perhaps most importantly, the SmartNIC market has repeatedly shown that hyperscalers — the only buyers at scale — prefer to design their own silicon (Google's custom NICs, Microsoft's Catapult/Azure FPGA program) rather than adopt external open designs, which limits the realistic deployment surface for a project like SCENIC.

The Paper